Simulation of Carbon Nanotube FETs for Power-Efficient Digital Circuits

Abstract

This work addresses the limitations of silicon scaling by exploring Carbon Nanotube FETs (CNTFETs) as alternatives. Schottky Barrier CNTFETs (SBCNTFETs) suffer from ambipolar currents, which reduce the Ion/Ioff ratio; this can be improved through optimised design parameters. A Double Gate (DG) structure is modelled to enhance gate control, achieving better Ion/Ioff ratio (5.55×105) and subthreshold swing (87.3mV/ decade). A mathematical model for DG-SBCNTFET is developed and validated with Nano TCAD ViDES simulations. Using optimised parameters, a DG-SBCNTFET-based 6T SRAM cell is designed and simulated in HSPICE, demonstrating 20% lower power dissipation compared to a conventional CNTFET SRAM cell without compromising stability.