Imran Ullah Khan, Somendra Shukla, Rani Kiran, Nupur Mittal, Mohd. Amir Ansari2026-03-112026-01-23979-8-3315-7746-9https://doi.org/10.1109/IITCEE67948.2026.11394352http://136.232.12.194:4000/handle/123456789/1700Published in: 2026 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE)This work addresses the limitations of silicon scaling by exploring Carbon Nanotube FETs (CNTFETs) as alternatives. Schottky Barrier CNTFETs (SBCNTFETs) suffer from ambipolar currents, which reduce the Ion/Ioff ratio; this can be improved through optimised design parameters. A Double Gate (DG) structure is modelled to enhance gate control, achieving better Ion/Ioff ratio (5.55×105) and subthreshold swing (87.3mV/ decade). A mathematical model for DG-SBCNTFET is developed and validated with Nano TCAD ViDES simulations. Using optimised parameters, a DG-SBCNTFET-based 6T SRAM cell is designed and simulated in HSPICE, demonstrating 20% lower power dissipation compared to a conventional CNTFET SRAM cell without compromising stability.en-USComputational modelingSimulationLogic gatesSRAM cellsMathematical modelsStability analysisCNTFETsPower dissipationCircuit stabilityIntegrated circuit modelingArticle