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Routing Congestion in VLSI Circuits :estimation and optimization Prashana Saxena, Rupesh S. Sheler and Sachin S. Sapatnekar [Text]

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Material type: Text

TextLanguage: English Publication details: New Delhi Springer 2010Description: 248p; 25cmISBN:

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Holdings
Item type	Current library	Call number	Copy number	Status	Notes	Date due	Barcode
RESERVE BOOKS	CENTRAL LIBRARY	621.395 SAX/R (Browse shelf(Opens below))	1	Not For Loan	050152		050152
TEXT BOOK	CENTRAL LIBRARY	621.395 SAX/R (Browse shelf(Opens below))	2	Available	050153		050153

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Previous	621.395 SAR/O Operational Amplifiers and Their Applications	621.395 SAR/V VLSI Design and EDATools	621.395 SAS/S Switching Theory for Logic Synthesis	621.395 SAX/R Routing Congestion in VLSI Circuits :estimation and optimization	621.395 TAU/F Fundamentals of Modern VLSI Devices	621.395 TAU/F Fundamentals of Modern VLSI Devices	621.395 TRI/L Linear Systems Analysis	Next

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