VHDL: coding and logic synthesis with synopsys Weng Fook Lee [Text]
Material type:
TextLanguage: English Publication details: London Academic press 2000Description: 392pSubject(s): DDC classification: - 621.392 LEE/V
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CENTRAL LIBRARY | 621.392 LEE/V (Browse shelf(Opens below)) | Not For Loan | 027223 | 027223 | ||
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CENTRAL LIBRARY | 621.392 LEE/V (Browse shelf(Opens below)) | Not For Loan | 027224 | 027224 | ||
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CENTRAL LIBRARY | 621.392 LEE/V (Browse shelf(Opens below)) | Available | 027221 | 027221 | ||
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TEXT BOOK
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CENTRAL LIBRARY | 621.392 LEE/V (Browse shelf(Opens below)) | Available | 027222 | 027222 |
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| 621.392 LEE/A Advanced Digital Logic Design: using verilog, state machines, and synthesis for FPGAs | 621.392 LEE/A Advanced Digital Logic Design: using verilog, state machines, and synthesis for FPGAs | 621.392 LEE/V VHDL: coding and logic synthesis with synopsys | 621.392 LEE/V VHDL: coding and logic synthesis with synopsys | 621.392 MAN/D Digital Design | 621.392 PAD/D Design Through Verilog HDL | 621.392 PAD/D Design Through Verilog HDL |
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