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Analytical Delay Model for Nano-Scale CMOS Inverter- Transmission Gate structure Mohammad Shueb Romi; Guided by Mohd. Yusuf Yasin & Naushad Alam

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Material type: Text

TextLanguage: English Publication details: Lucknow Integral University 2014Description: 52p; 30cmSubject(s):

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Item type	Current library	Collection	Call number	Status	Notes	Date due	Barcode
Dissertation-Master Degree	CENTRAL LIBRARY	ELECTRICAL	621.3 MOH/A (Browse shelf(Opens below))	Not For Loan	Electrical Engineering		DM1065

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Previous	621.3 MIS/P Performance of Orthogonal Frequency Division Multiplexing in Mobile Radio Channel	621.3 MIS/P Performance Evaluation of SPIHT and Listless SPIHT	621.3 MIT/S Simulation of High Performance Current Controlled Conveyor(CCCII) & its Applications Based on 350nm CMOS Technology	621.3 MOH/A Analytical Delay Model for Nano-Scale CMOS Inverter- Transmission Gate structure	621.3 MOH/D Development Methodology of on-chip Charge pump	621.3 MOH/D Design of Combinational Circuit using Quantum Dot Cellular Automata	621.3 MOH/D Design of CORDIC Hardware Efficient Shift-And-Add Algorithm for DSP Processors on FPGA Device using VHDL	Next

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