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Power and Delay Optimized edge Triggered Flip-Flop for Low power Microcontrollers Sameer Gull Alie; Guided by Tarana afrin Chandel

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TextLanguage: English Publication details: Lucknow Integral University 2014Description: 60p; 30cmSubject(s):

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Holdings
Item type	Current library	Collection	Call number	Status	Notes	Date due	Barcode
Dissertation-Master Degree	CENTRAL LIBRARY	ELECTRICAL	621.3 SAM/P (Browse shelf(Opens below))	Not For Loan	Electrical Engineering		DM1040

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Previous	621.3 SAI/R Realization And Study of Defferential Mode Circuits and Their Applications	621.3 SAI/S Scalable ACC-DCT Based Video Compression using Up/Down Sampling Method	621.3 SAJ/F FPGA Design of 4*4 Crossbar Switch for Multiprocessor System on Chip (MPSoC) Using Round Robin Arbitration	621.3 SAM/P Power and Delay Optimized edge Triggered Flip-Flop for Low power Microcontrollers	621.3 SAN/D Design and Analysis of low Power Full Adder	621.3 SAX/I Image Compression using Neural Network with Levenberg-Marquardt Algorithm	621.3 SHA/D Design of Delay-Efficient Configurable Booth Multiplier for High Speed Applications	Next

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