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Design and Simulation of Low Power Array Multiplier Kalpana Gupta; Guided by Shailendra Kumar

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Material type: Text

TextLanguage: English Publication details: Lucknow Integral University 2012Description: 77p;m 30cmSubject(s):

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Holdings
Item type	Current library	Collection	Call number	Status	Notes	Date due	Barcode
Dissertation-Master Degree	CENTRAL LIBRARY	ELECTRICAL	621.3 GUP/D (Browse shelf(Opens below))	Not For Loan	Electrical Engineering		DM0697

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Previous	621.3 FIR/L Low voltage Low Power Redesign of CCII in 45nm COMS Technology and its Analog & Digital Applications	621.3 GAU/O Optimisation of Fuzzy Logic MPPT Controller using Particle Swarm Optimisation Techniques	621.3 GUP/D Design and Simulation of low Power 16 Bit Carry Skip Adder	621.3 GUP/D Design and Simulation of Low Power Array Multiplier	621.3 HAR/D Design of Image Editing portal using Matlab	621.3 HAS/S Simulation of high Performance Second Generation CMOS Current Controlled Conveyors(CCCIIs) & Their Application	621.3 HEE/M Modelling abd Simulation of Bridgeless Power Factors Correction Boost Converter	Next

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