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Design and Soft Implementation of N-Bit SRT Divider on FPGA Through VHDL Jyotika Kumari; Guided by M.Y.Yasin

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TextLanguage: English Publication details: Lucknow Integral University 2015Description: 108p; 30cmSubject(s):

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Item type	Current library	Collection	Call number	Status	Notes	Date due	Barcode
Dissertation-Master Degree	CENTRAL LIBRARY	ELECTRICAL	621.3 JYO/D (Browse shelf(Opens below))	Not For Loan	Electrical Engineering		DM1172

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Previous	621.3 IMR/C Clock Period Minimization Through Retiming Technique	621.3 IRS/S Solid State Thermoelectricity Generator and its use in Energy Recycling	621.3 JAI/S Speed and Torque Control of a Permanent Magnet Brush less DC Motor	621.3 JYO/D Design and Soft Implementation of N-Bit SRT Divider on FPGA Through VHDL	621.3 KAV/D Detection f Rapid Eye Movement Behaviour Disorder using Short-Time Frequency Analysis on EEG Signal	621.3 KHA/C Comparative Study of Clocked and Un-Clocked CCCII and Its Applications	621.3 KHA/D Design of VGA Controller using VHDL for LCD Display Using FPGA	Next

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